This is is for our Beijing headquartered Client who cater to leading Semiconductor Companies in the world
Validation Engineers ( for 6 months contract) location: Bangalore, for 6+ Months contract
Compensation: Negotiable
Job Description:
4-10 years’ experience in verification. Worked on coverage driven module verification.
Strong in System Verilog, UVM
Sound experience in testbench (stimulus, agent, monitor, checker) development.
failure debugging with Verdi & log file.
Worked in the verification having c based reference model inside the testebench
Experience with assertion development.
Familiar with the EDA tools IUS, VCS, Verdi etc.
Exposure in scripting(perl, Python).
Good team player. Need to interact with the designers and other verification engineers proactively.
Prior experience with video domain is added advantage.
Have exposure to the other verification tasks : gate level simulation, Power aware simulation, formal verification, sub-system verification, firmware verification